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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. 00e 10/25/05 IS93C46D issi ? copyright ? 2005 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 1-kbit serial electrically erasable prom advanced information november 2005 functional block diagram cs sk d in d out dummy bit r/w amps data register address register address decoder write enable high voltage generator instruction decode, control, and clock generation eeprom array 128x8 64x16 instruction register features ? industry-standard microwire interface ? non-volatile data storage ? wide voltage operation: vcc = 1.8v to 5.5v ? full ttl compatible inputs and outputs ? auto increment for efficient data dump ? user configured memory organization ? by 16-bit or by 8-bit ? hardware and software write protection ? defaults to write-disabled state at power-up ? software instructions for write-enable/disable ? enhanced low voltage cmos e 2 prom technology ? versatile, easy-to-use interface ? self-timed programming cycle ? automatic erase-before-write ? programming status indicator ? word and chip erasable ? chip select enables power savings ? durable and reliable ? 40-year data retention after 1m write cycles ? 1 million write cycles ? unlimited read cycles ? schmitt-trigger inputs ? lead-free available description the IS93C46D is a 1kb non-volatile, issi ? serial eeprom. it is fabricated using an enhanced cmos design and process. the IS93C46D contains power-efficient read/write memory, and organization of 128 bytes of 8 bits or 64 words of 16 bits. when the org pin is connected to vcc or left unconnected, x16 is selected; when it is connected to ground, x8 is selected. an instruction set defines the operation of the devices, including read, write, and mode-enable functions. to protect against inadvertent data modification, all erase and write instructions are accepted only while the device is write-enabled. a selected x8 byte or x16 word can be modified with a single write or erase instruction. additionally, the two instructions write all or erase all can program the entire array. once a device begins its self-timed program procedure, the data out pin (dout) can indicate the ready/ busy status by raising chip select (cs). the self- timed write cycle includes an automatic erase- before-write capability. the device can output any number of consecutive bytes/words using a single read instruction.
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00e 10/25/05 IS93C46D issi ? pin configurations 8-pin jedec soic ?g? 8-pin jedec soic ?gr? pin descriptions cs chip select sk serial data clock d in serial data input d out serial data output org organization select nc not connected vcc power gnd ground instruction begins with a start bit of the logical ?1? or high. following this are the opcode (2 bits), address field (6 or 7 bits), and data, if appropriate. the clock signal may be held stable at any moment to suspend the device at its last state, allowing clock- speed flexibility. upon completion of bus communication, cs would be pulled low. the device then would enter standby mode if no internal programming is underway. read (read) the read instruction is the only instruction that outputs serial data on the d out pin. after the read instruction and address have been decoded, data is transferred from the selected memory register into a serial shift register. (please note that one logical ?0? bit precedes the actual 8 or 16-bit output data string.) the output on d out changes during the low-to-high transitions of sk (see figure 3). low voltage read the IS93C46D has been designed to ensure that data read operations are reliable in low voltage environments. they provide accurate operation with vcc as low as 1.8v. auto increment read operations in the interest of memory transfer operation applications, the IS93C46D has been designed to output a continuous stream of memory content in response to a single read operation instruction. to utilize this function, the system asserts a read instruction specifying a start location ad- dress. once the 8 or 16 bits of the addressed register have been clocked out, the data in consecutively higher address locations is output. the address will wrap around continu- ously with cs high until the chip select (cs) control pin is brought low . this allows for single instruction data dumps to be executed with a minimum of firmware overhead. applications the IS93C46D is very popular in many applications which require low-power, low-density storage. applications using this device include industrial controls, networking, and numerous other consumer electronics. endurance and data retention the IS93C46D is designed for applications requiring up to 1m programming cycles (write, wrall, erase and eral). it provides 40 years of secure data retention without power after the execution of 1m programming cycles. device operations the IS93C46D is controlled by a set of instructions which are clocked-in serially on the din pin. before each low-to-high transition of the clock (sk), the cs pin must have already been raised to high, and the din value must be stable at either low or high. each 1 2 3 4 8 7 6 5 cs sk d in d out vcc nc org gnd 1 2 3 4 8 7 6 5 nc vcc cs sk org gnd d out d in 1 2 3 4 8 7 6 5 cs sk d in d out vcc nc org gnd (rotated) 8-pin dip, 8-pin tssop
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. 00e 10/25/05 IS93C46D issi ? write all (wrall) the write all (wrall) instruction programs all registers with the data pattern specified in the instruction. as with the write instruction, the falling edge of cs must occur to initiate the self-timed programming cycle. if cs is then brought high after a minimum wait of 200 ns (t cs ), the d out pin indicates the ready/ busy status of the chip (see figure 6). vcc is required to be above 4.5v for wrall to function properly. write disable (wds) the write disable (wds) instruction disables all programming capabilities. this protects the entire device against acci- dental modification of data until a wen instruction is executed. (when vcc is applied, this part powers up in the write disabled state.) to protect data, a wds instruction should be executed upon completion of each programming operation. erase register (erase) after the erase instruction is entered, cs must be brought low. the falling edge of cs initiates the self-timed internal programming cycle. bringing cs high after a minimum of t cs , will cause d out to indicate the read/ busy status of the chip: a logical ?0? indicates programming is still in progress; a logical ?1? indicates the erase cycle is complete and the part is ready for another instruction (see figure 8). erase all (eral) full chip erase is provided for ease of programming. erasing the entire chip involves setting all bits in the entire memory array to a logical ?1? (see figure 9). vcc is required to be above 4.5v for eral to function properly. write enable (wen) the write enable (wen) instruction must be executed before any device programming (write, wrall, erase, and eral) can be done. when vcc is applied, this device powers up in the write disabled state. the device then remains in a write disabled state until a wen instruction is executed. thereafter, the device remains enabled until a wds instruction is executed or until vcc is removed. (see figure 4.) (note: chip select must remain low until vcc reaches its operational value.) write (write) the write instruction includes 8 or 16 bits of data to be written into the specified register. after the last data bit has been applied to d in , and before the next rising edge of sk, cs must be brought low. if the device is write-enabled, then the falling edge of cs initiates the self-timed program- ming cycle (see wen). if cs is brought high, after a minimum wait of 200 ns (5v operation) after the falling edge of cs (t cs ) d out will indicate the ready/ busy status of the chip. logical ?0? means programming is still in progress; logical ?1? means the selected register has been written, and the part is ready for another instruction (see figure 5). the ready/ busy status will not be available if: a) the cs input goes high after the end of the self-timed programming cycle, t wp ; or b) simultaneously cs is high, din is high, and sk goes high, which clears the status flag. instruction set - IS93C46D (1kb) 8-bit organization 16-bit organization (org = gnd) (org = vcc) instruction (2) start bit op code address (1) input data address (1) input data read 1 10 (a 6 -a 0 )? (a 5 -a 0 )? wen (write enable) 1 00 11xxxxx ? 11xxxx ? write 1 01 (a 6 -a 0 )(d 7 -d 0 )(a 5 -a 0 )(d 15 -d 0 ) wrall (write all registers) 1 00 01xxxxx (d 7 -d 0 ) 01xxxx (d 15 -d 0 ) wds (write disable) 1 00 00xxxxx ? 00xxxx ? erase 1 11 (a 6 -a 0 )? (a 5 -a 0 )? eral ( erase all registers) 1 00 10xxxxx ? 10xxxx ? notes: 1. x = don't care bit. 2. if the number of bits clocked-in does not match the number corresponding to a selected command, all extra trailing bits are i gnored, and write, wrall, erase, eral are also ignored, and read, wen, wds are accepted.
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00e 10/25/05 IS93C46D issi ? capacitance symbol parameter conditions max. unit c in input capacitance v in = 0v 5 pf c out output capacitance v out = 0v 5 pf operating range range ambient temperature v cc industrial ?40c to +85c 1.8v to 5.5v automotive ?40c to +125c 2.5v to 5.5v note: issi offers industrial grade for commercial applications (0 o c to +70 o c) absolute maximum ratings (1) symbol parameter value unit v s supply voltage ?0.5 to +6.5 v v p voltage on any pin ?0.5 to vcc + 0.5 v t bias temperature under bias ?55 to +125 c t stg storage temperature ?65 to +150 c i out output current 5 ma notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. 00e 10/25/05 IS93C46D issi ? dc electrical characteristics t a = ?40c to +85c for industrial and ?40c to +125c for automotive. symbol parameter test conditions vcc min. max. unit v ol2 output low voltage i ol = 100 a 1.8v to 2.7v ? 0.2 v v ol1 output low voltage i ol = 2.1ma 2.7v to 5.5v ? 0.4 v v oh2 output high voltage i oh = ?100 a 1.8v to 2.7v v cc ? 0.2 ? v v oh1 output high voltage i oh = ?400 a 2.7v to 5.5v 2.4 ? v v ih input high voltage 1.8v to 2.7v 0.7 x v cc v cc +1 v 2.7v to 5.5v 2.0 v cc +1 v il input low voltage 1.8v to 2.7v ?0.3 0.2 x v cc v 2.7v to 5.5v ?0.3 0.8 i li input leakage v in = 0v to v cc (cs, sk, d in ,org) 0 2.5 a i lo output leakage v out = 0v to v cc , cs = 0v 0 2.5 a notes: automotive grade devices in this table are tested with vcc = 2.5v to 5.5v and 4.5v to 5.5v. an operation with vcc <2.5v is not specified. power supply characteristics t a = ?40c to +85c for industrial, ?40c to +125c for automotive. symbol parameter test conditions vcc min. typ. max. unit i cc 1 vcc read supply current cs = v ih , sk = 1 mhz, cmos input levels 1.8v ? 0.1 1 ma cs = v ih , sk = 2 mhz, cmos input levels 2.5v ? 0.2 1 ma cs = v ih , sk = 2 mhz, cmos input levels 5.0v ? 0.5 2 ma i cc 2 vcc write supply current cs = v ih , sk = 1 mhz, cmos input levels 1.8v ? 0.5 1 ma cs = v ih , sk = 2 mhz, cmos input levels 2.5v ? 1 2 ma cs = v ih , sk = 2 mhz, cmos input levels 5.0v ? 2 3 ma i sb 1 standby current cs = gnd, sk = gnd 1.8v ? 0.1 1 a org = vcc or floating (x16) 2.5v ? 0.1 2 a d in = vcc or gnd 5.0v ? 0.2 4 a i sb 2 standby current cs = gnd, sk = gnd 1.8v ? 6 10 a org = gnd (x8) 2.5v ? 6 10 a d in = vcc or gnd 5.0v ? 10 15 a
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00e 10/25/05 IS93C46D issi ? ac electrical characteristics t a = ?40c to +85c for industrial symbol parameter test conditions min. max. unit f sk sk clock frequency 1.8v vcc < 2.5v 0 1 mhz 2.5v vcc < 4.5v 0 2 mhz 4.5v vcc 5.5v 0 3 mhz t skh sk high time 1.8v vcc < 2.5v 250 ? ns 2.5v vcc < 4.5v 200 ? ns 4.5v vcc 5.5v 200 ? ns t skl sk low time 1.8v vcc < 2.5v 250 ? ns 2.5v vcc < 4.5v 200 ? ns 4.5v vcc 5.5v 100 ? ns t cs minimum cs low time 1.8v vcc < 2.5v 250 ? ns 2.5v vcc < 4.5v 200 ? ns 4.5v vcc 5.5v 200 ? ns t css cs setup time relative to sk 1.8v vcc < 2.5v 200 ? ns 2.5v vcc < 4.5v 100 ? ns 4.5v vcc 5.5v 50 ? ns t dis din setup time relative to sk 1.8v vcc < 2.5v 100 ? ns 2.5v vcc < 4.5v 50 ? ns 4.5v vcc 5.5v 50 ? ns t csh cs hold time relative to sk 1.8v vcc < 2.5v 0 ? ns 2.5v vcc < 4.5v 0 ? ns 4.5v vcc 5.5v 0 ? ns t dih din hold time relative to sk 1.8v vcc < 2.5v 50 ? ns 2.5v vcc < 4.5v 50 ? ns 4.5v vcc 5.5v 50 ? ns t pd1 output delay to ?1? ac test 1.8v vcc < 2.5v ? 400 ns 2.5v vcc < 4.5v ? 200 ns 4.5v vcc 5.5v ? 100 ns t pd0 output delay to ?0? ac test 1.8v vcc < 2.5v ? 400 ns 2.5v vcc < 4.5v ? 200 ns 4.5v vcc 5.5v ? 100 ns t sv cs to status valid ac test 1.8v vcc < 2.5v ? 400 ns 2.5v vcc < 4.5v ? 200 ns 4.5v vcc 5.5v ? 200 ns t df cs to dout in 3-state ac test, cs=vil 1.8v vcc < 2.5v ? 100 ns 2.5v vcc < 4.5v ? 100 ns 4.5v vcc 5.5v ? 100 ns t wp write cycle time 1.8v vcc < 2.5v ? 10 ms 2.5v vcc < 4.5v ? 5ms 4.5v vcc 5.5v ? 5ms notes: 1. c l = 100pf
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. 00e 10/25/05 IS93C46D issi ? ac electrical characteristics t a = ?40c to +125c for automotive symbol parameter test conditions min. max. unit f sk sk clock frequency 2.5v vcc < 4.5v 0 2 mhz 4.5v vcc 5.5v 0 3 mhz t skh sk high time 2.5v vcc < 4.5v 200 ? ns 4.5v vcc 5.5v 200 ? ns t skl sk low time 2.5v vcc < 4.5v 200 ? ns 4.5v vcc 5.5v 100 ? ns t cs minimum cs low time 2.5v vcc < 4.5v 200 ? ns 4.5v vcc 5.5v 200 ? ns t css cs setup time relative to sk 2.5v vcc < 4.5v 100 ? ns 4.5v vcc 5.5v 50 ? ns t dis din setup time relative to sk 2.5v vcc < 4.5v 50 ? ns 4.5v vcc 5.5v 50 ? ns t csh cs hold time relative to sk 2.5v vcc < 4.5v 0 ? ns 4.5v vcc 5.5v 0 ? ns t dih din hold time relative to sk 2.5v vcc < 4.5v 50 ? ns 4.5v vcc 5.5v 50 ? ns t pd1 output delay to ?1? ac test 2.5v vcc < 4.5v ? 200 ns 4.5v vcc 5.5v ? 100 ns t pd0 output delay to ?0? ac test 2.5v vcc < 4.5v ? 200 ns 4.5v vcc 5.5v ? 100 ns t sv cs to status valid ac test 2.5v vcc < 4.5v ? 200 ns 4.5v vcc 5.5v ? 200 ns t df cs to dout in 3-state ac test, cs=vil 2.5v vcc < 4.5v ? 100 ns 4.5v vcc 5.5v ? 100 ns t wp write cycle time 2.5v vcc < 4.5v ? 5ms 4.5v vcc 5.5v ? 5ms notes: 1. c l = 100pf
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00e 10/25/05 IS93C46D issi ? ac waveforms figure 2. synchronous data timing figure 3. read cycle timing d in d out cs t cs 0 dm d0 110an a0 * address pointer cycles to the next register * notes: to determine address bits an-a0 and data bits dm-do, see instruction set for the specific device. t skh t t css t skl t csh cs sk d in d out (read) d out (write) (wrall) (erase) (eral) status valid t dis t dih t pd0 t sv t pd1 t df t df
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. 00e 10/25/05 IS93C46D issi ? figure 5. write (write) cycle timing notes: 1. after the completion of the instruction (d out is in ready status) then it may perform another instruction. if device is in busy status (d out indicates busy status) then attempting to perform another instruction could cause device malfunction. 2. to determine address bits a n -a 0 and data bits d m -d 0 , see instruction set for the specific device. d in d out cs t cs 11 0ana0 dm d0 busy ready t sv t df t wp d in d out = 3-state cs t cs 1 1 00 1 ac waveforms figure 4. write enable (wen) cycle timing
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00e 10/25/05 IS93C46D issi ? figure 7. write disable (wds) cycle timing d in cs 10 0 t cs 00 d out = 3-state d in d out cs 11 0 t cs dm d0 busy ready t sv t wp 00 notes: 1. after the completion of the instruction (d out is in ready status) then it may perform another instruction. if device is in busy status (d out indicates busy status) then attempting to perform another instruction could cause device malfunction. 2. to determine data bits d m -d 0 , see instruction set for the appropriate device. ac waveforms figure 6. write all (wrall) cycle timing
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. 00e 10/25/05 IS93C46D issi ? figure 9. erase all (eral) cycle timing d in d out cs 1 t cs busy ready t sv t df t wp 11 an-1 a0 an notes: to determine data bits an - a0, see instruction set for the appropriate device. d in d out cs 0 10 t cs busy ready t sv t df t wp 1 0 ac waveforms figure 8. erase (register erase) cycle timing note for figures 8 and 9: after the completion of the instruction (d out is in ready status) then it may perform another instruction. if device is in busy status (d out indicates busy status) then attempting to perform another instruction could cause device malfunction.
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. 00e 10/25/05 IS93C46D issi ? ordering information automotive range: -40oc to +125oc, lead-free voltage range order part no. package 2.5v to 5.5v IS93C46D-3pla3 300-mil plastic dip IS93C46D-3grla3 soic jedec ordering information industrial range: -40oc to +85oc voltage range order part no. package 1.8v to 5.5v IS93C46D-2pi 300-mil plastic dip IS93C46D-2gi soic (rotated) jedec IS93C46D-2gri soic jedec IS93C46D-2zi 169-mil tssop ordering information industrial range: -40oc to +85oc, lead-free voltage range order part no. package 1.8v to 5.5v IS93C46D-2pli 300-mil plastic dip IS93C46D-2gli soic (rotated) jedec IS93C46D-2grli soic jedec IS93C46D-2zli 169-mil tssop
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. d 02/14/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 300-mil plastic dip package code: n,p a d 1 b n seating plane c a1 e a l e b1 s e1 e s for 32-pin only b2 millimeters inches sym. min. max. min. max. n0. leads 8 a 3.68 4.57 0.145 0.180 a1 0.38 ? 0.015 ? b 0.36 0.56 0.014 0.022 b1 1.14 1.52 0.045 0.060 b2 0.81 1.17 0.032 0.046 c 0.20 0.33 0.008 0.013 d 9.12 9.53 0.359 0.375 e 7.62 8.26 0.300 0.325 e1 6.20 6.60 0.244 0.260 e a 8.13 9.65 0.320 0.380 e 2.54 bsc 0.100 bsc l 3.18 ? 0.125 ? s 0.64 0.762 0.025 0.030 notes: 1. controlling dimension: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
packaging information issi ? integrated silicon solution, inc. ? 1-800-379-4774 2 rev. c 10/03/01 150-mil plastic sop package code: g, gr d seating plane b e c 1 n e a1 a h l notes: 1. controlling dimension: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 150-mil plastic sop (g, gr) symbol min max min max ref. std. inches mm no. leads 8 8 a ? 0.068 ? 1.73 a1 0.004 0.009 0.1 0.23 b 0.013 0.020 0.33 0.51 c 0.007 0.010 0.18 0.25 d 0.189 0.197 4.8 5 e 0.150 0.157 3.81 3.99 h 0.228 0.245 5.79 6.22 e 0.050 bsc 1.27 bsc l 0.020 0.035 0.51 0.89
integrated silicon solution, inc. packaging information issi ? thin shrink small outline tssop package code: z (8 pin, 14 pin) rev b 02/01/02 tssop (z) ref. std. jedec mo-153 no. leads 8 millimeters inches symbol min max min max a ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 d 2.90 3.10 0.114 0.122 e1 4.30 4.50 0.169 0.177 e 6.40 bsc 0.252 bsc e 0.65 bsc 0.026 bsc l 0.45 0.75 0.018 0.030 ?8 ?8 tssop (z) ref. std. jedec mo-153 no. leads 14 millimeters i nches symbol min max min max a ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.031 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.10 0.193 0.201 e1 4.30 4.50 0.170 0.177 e 6.40 bsc 0.252 bsc e 0.65 bsc 0.026 bsc l 0.45 0.75 0.0177 0.0295 ?8 ? 8 d b e e1 a2 e c a a1 l 1 n n/2 ssi reserves the right to make changes to its products at any time without notice in order to improve design and supply the bes t possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2002, integrated silicon solution, inc.

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